Open source design verification is a key enabler for more collaborative flows in ASIC development. The RISC-V DV framework, based on an open source instruction set generator developed by Google, is enabling end-to-end verification flows for RISC-V CPUs.  The generator supports all RISC-V ISA extensions, and can be configured to generate highly random tests for various RISC-V processors. This talk will cover the fundamentals of the flow and recent developments including Bit-manipulation extension, Vector extension, multi-cores verification, functional coverage model, python based random instruction generator etc.  Learn more about the technology and its latest developments in Tao Liu’s talk.